1. Field of Invention
The present invention relates to a method of fabricating a via hole. More particularly, the present invention relates to a method of fabricating an unlanded via hole.
2. Description of Related Art
Due to the increasingly high integration of ICs, chips simply cannot provide sufficient areas for interconnection manufacturing. Therefore, in accord with the increased interconnect manufacturing requirements of miniaturized MOS transistors, it is increasingly necessary for IC manufacturing to adopt a design with more than two metal layers. In particular, a number of function-complicated products, such as microprocessors, even require 4 or 5 metal layers to complete the internal connections. Generally, an inter-metal dielectric (IMD) layer is used to electrically isolate two adjacent metal layers from each other. Moreover, a conductive layer used to electrically connect the two adjacent metal layers is called a via plug in the semiconductor industry.
With the decrease of wire width in ICs and the increase of integration of ICs, misalignment easily occurs as the dielectric layer is patterned to form the via hole. Misalignment causes the dielectric layer to be etched through by etching gas; thus, a landed via hole cannot be formed and the subsequently formed via plug is electrically coupled to the conductive region in the substrate. Therefore device failure results.
FIG. 1 is a schematic, cross-sectional view of an unlanded via hole. A semiconductor substrate 100 is provided. Devices (not shown) are preformed on the substrate 100. A planarization process is performed on the substrate. An aluminum layer is formed on the substrate 100 by sputtering or chemical vapor deposition (CVD). A titanium layer is formed on the aluminum layer by DC magnetron sputtering to serve as a glue layer. A nitridation is performed on the titanium layer to form a titanium nitride layer as a barrier layer. A glue/barrier layer made of titanium/titanium nitride serves as an anti-reflection coating (ARC) layer.
A patterned photoresist layer is formed on the anti-reflection coating layer. Using the patterned photoresist layer as a mask, the ARC layer and the aluminum layer are anisotropically etched to form a patterned ARC layer 108 and a conductive line 102 of aluminum. The patterned ARC layer 108 includes a barrier layer 106 of titanium nitride and a glue layer 104 of titanium. Then the photoresist layer is removed. However, after the anisotropically etching process, the experimental result shows the width of the ARC layer 108 on the conductive layer 102 is somewhat greater than that of the conductive line of aluminum. In other words, the dimension of the ARC layer 108 is bigger than that of the conductive line 102. Consequently, the conductive line 102 of aluminum is completely covered by the ARC layer 108.
A planarized silicon oxide layer 112 is formed over the substrate 100 by chemical-mechanical polishing (CMP) to cover the ARC layer 108 and the conductive line 102. Using the ARC layer 108 as a stop on ARC (SOA), the dielectric layer 112 is defined by photolithography and etching to form a via hole 114 in the dielectric layer 112 to expose a portion of a surface and sidewalls of the ARC layer 108. The width of the ARC layer 108 on the conductive layer 102 is somewhat greater than that of the conductive line so that the ARC layer provides a shield for the conductive line 102. Hence after the anisotropic etching process is performed with the ARC layer 108 serving as a SOA to form the unlanded via hole, a portion of the dielectric layer 112 is still left between the conductive line and the unlanded via hole 114. Consequently, the unlanded via hole 114 just contacts the ARC layer 108 and cannot make contact with the conductive line 102 of aluminum so as to increase contact resistance generated between the conductive line 102 and a subsequently formed plug in the unlanded via hole 114. Hence RC delay time and device performance are affected.